Infrared detector formats

Infrared detectors are available as single element detectors in circular, rectangular, cruciform, and other geometries for reticle systems, as linear arrays, and as 2D focal plane arrays

Single element detectors are normally frontside illuminated and wire bonded devices. Linear and 2D arrays may be fabricated with a variety of device and signal output architectures.

First generation linear arrays were usually frontside illuminated, with the detector signal output connected by wire bonding to each element in the array. The signal from each element was then brought out of the vacuum package and connected to an individual room temperature preamplifier prior to interfacing with the imaging system display. Gain adjustments were usually made in the preamplifier circuitry. This approach limited first generation linear arrays to less than two hundred elements.

Second generation arrays, both linear and 2D, are frequently backside illuminated through a transparent substrate. Several alternative focal plane architectures are illustrated in the graph below.

Figure (a) illustrates a detector array which is electrically connected directly to an array of preamplifiers and/or switches called a readout. The electrical connection is made with indium "bumps" which provide a soft metal interconnect for each pixel. This arrangement, commonly referred to as a "direct hybrid", facilitates the interconnection of large numbers of pixels to individual preamplifiers coupled with row and column multiplexers.

Indirect hybrid configurations (b) may be used with large linear arrays to interface the detector with a substrate having a similar thermal coefficient of expansion. These hybrids may also be used for serial hybridization, allowing the detector to be tested prior to committing the readout, and/or to accommodate readout unit cells having dimensions larger than the detector unit cell, increasing the charge storage capacity and thereby extending the dynamic range. Readouts and detectors are electrically interconnected by a patterned metal bus on a fanout substrate.

Monolithic detector arrays (c) have integrated detector and readout functions. Generally, in these arrays, the command and control signal processing electronics are adjacent to the detector array, rather than underneath. In this case, the signal processing circuits may be connected to the detector by wire bonds. In the monolithic configuration it is not necessary for the signal processing circuits to be on the same substrate as the detector/readout (as shown in the figure) or at the same temperature as the detector. Monolithic PtSi detector arrays can be made with signal processing incorporated on the periphery of the detector/readout chip through the use of silicon-based detector technology.

Z technology, as illustrated in figure (d), provides extended signal processing real estate for each pixel in the readout chip by extending the structure in the orthogonal direction. In the approach illustrated, stacked, thinned readout chips are glued together, and the detector array is connected to the edge of this signal processing stack with indium.

Finally, a "Loophole" approach, as illustrated in figure (e), relies on thinning the detector material after adhesively bonding it to the silicon readout. Detector elements are connected to the underlying readout with vias, which are etched through the detector material to contact pads on the readout and metallized.